Traditionally, digital signals are transmitted sequentially: each bit is sent for a constant amount of time and during a precisely defined interval of time. Typically, the time interval is defined for the transmitter by an electronic metronome known to those skilled in the art as a "clock signal" (hereinafter "clock"). A clock is typically generated by a crystal oscillator and is often embodied as electric squarewave signal with constant frequency and a 50% duty cycle.
To assure that the receiver correctly interprets the incoming data signals, the receiver must selectively read the incoming data signals only at instants when the signals have stabilized and not when they are undergoing transition. This requires the receiver to know when the incoming data signals are stable and when they are not. Advantageously, the receiver also has an electronic metronome, synchronized to the incoming data signal which dictates "read now-wait, read now-wait, read now-wait. . . ." Typically, the receiver has information regarding the frequency or frequencies of the transmitter's clock and has a clock with that same frequency. The receiver's clock, however, will, without more, bear no phase relationship to the incoming data signal and thus the receiver will have no synchronized metronome to assist it in reading the incoming data signal.
To generate a clock which is synchronized with respect to the incoming data signal, the receiver may advantageously utilize a "clock recovery system". At least two clock recovery techniques are currently known. First, the transmitter's clock may be transmitted to the receiver on a communication channel in parallel to the channel carrying the incoming data signals. The receiver can then use this second channel as a clock with proper phase to determine when to read the data on the first channel. This technique, however, is disadvantageous in that it requires additional hardware, e.g., the extra communication channel, and is subject to phase skew between the transmitted clock and the incoming data signal.
Alternately, the phase of the incoming data signals may be recovered directly from the incoming data signals themselves because the incoming data signals carry the information needed to discern its phase. At least two techniques are known which recover the phase of the incoming data signals from the incoming data signals themselves.
The first is the open-loop clock recovery system representatively taught by I. Dorros et al., An Experimental 224 Mb/s Digital Repeatered Line, The Bell System Technical Journal, Vol. 45, No. 7, pp. 993-1043 (September 1966). Open-loop systems are characterized by a highQ, narrow bandpass filter, e.g., a SAW filter, yet may be disadvantageous in that they typically require expensive nonintegrated components, hundreds of incoming data signal transitions to reach steady state and may be susceptible to temperature variations and age.
The second is the closed-loop clock recovery system. A representative closed-loop clock recovery system is taught by R. R. Cordell et al. in A 50 MHz Phase and Frequency-Locked Loop, IEEE Journal of Solid State Circuits, Vol. SC14, No. 6, pp. 1003-1010 (December 1979). Closed-loop systems are characterized by a phase-locked loop which attempts to lock onto the phase of the incoming data signal. While closed-loop recovery systems are self adjusting, thus mitigating temperature and aging effects, and can be easily integrated, they are disadvantageous in typically requiring hundreds of incoming data signal transitions to reach steady state.
While these clock recovery mechanisms may be satisfactory for non-burst mode signals which have some signal being constantly transmitted, they may be disadvantageous for burst mode signals in which arbitrary phase changes may exist between consecutive packets of the signal.
U.S. Pat. No. 5,237,290, which is incorporated by reference as if set forth herein in its entirety, provides a method and apparatus for recovering the phase of a signal while avoiding many of the costs and restrictions associated with prior apparatus and methods. The system described therein is ideally suited for use with burst mode signals in that it typically generates a recovered clock more quickly than other methods in the prior art. These results are obtained by feeding an incoming data signal into a gated oscillator while the complement of the incoming data signal is fed into a matching gated oscillator. The respective outputs of the two oscillators are fed into a NOR gate. When the gated oscillators are designed to oscillate at the frequency of the incoming data signal, the output waveform from the NOR gate will be a continuous clock that has a bounded phase relationship with respect to the incoming data signal, i.e., the recovered clock and the incoming data signal will have the same frequency and their relative phase will remain within a given range.
Disadvantageously, the system disclosed in U.S. Pat. No. 5,237,290 can only operate at a single frequency.